Senior Director Corporate Marketing
As Senior Director of the Global Customer Group at KLA-Tencor, Robert Cappel works with customers to understand their current and future requirements, while aiding KLA-Tencor in delivering solutions to meet those requirements.Cappel has 26 years of experience in the semiconductor industry with an emphasis on process control. During his first 10 years in the industry, he worked in process engineering and yield management roles at Dupont Tau Labs and Digital Equipment Corporation. At KLA-Tencor, he has worked in both technical and strategic marketing roles in the optical and e-beam inspection groups. Cappel’s interest in semiconductor technologies grew while he was completing his Bachelor of Science degree in Imaging Science at Rochester Institute of Technology. The author of 14 technical papers, Cappel has written about yield management techniques, e-beam inspection applications and the value of yield management. He has also presented on yield management strategies at conferences including Institute of Electrical and Electronics Engineers (IEEE), the International Symposium on Semiconductor Manufacturing (ISSM), and KLA-Tencor’s Yield Management Seminars.
William T. Chen
ASE Fellow and Senior Technical Advisor
Bill received his engineering education at University of London (B.Sc), Brown University (M.Sc) and Cornell University (PhD). He joined IBM Corporation at Endicott New York in 1963.
At IBM, he worked in a broad range of IBM microelectronic packaging products. He received IBM Division President Award for his leadership and innovation in Predictive Modelling on IBM products. He was elected to the IBM Academy of Technology for his contributions to IBM Products and Packaging Technologies. He retired from IBM in 1997. He joined the Institute of Materials Research and Engineering (IMRE) in Singapore, to initiate research in microelectronic packaging materials and processes. He was appointed to the position Director of the Institute (IMRE) steering the growth in people, funding and research facilities and research direction for IMRE to become the leading materials science and engineering research center in the ASEAN region. In 2001 he joined ASE Group, where he holds the position of ASE Fellow and Senior Technical Advisor. In this assignment he has responsibilities for guidance to technology strategic directions for ASE Group.
He is Senior Past President of the IEEE/CPMT Society. He is the Co-Chair of the ITRS Assembly and Packaging Roadmap Technical Working Group. He is chair of the Semicon West Packaging Committee. He has been elected to a member of the iNEMI Board. He is a member of the Technology Committee of GSA.
He has been elected to Fellow of IEEE and Fellow of ASME. He has served as an Associate Editor of ASME Journal of Electronic Packaging, and IEEE/CPMT Transactions.Prior to joining the ASE, Bill was the Director at the Institute of Materials Research & Engineering in Singapore. He worked for over thirty years at IBM Corporation. He is the co-chair of the ITRS Assembly Packaging Technical Working Group. He is a board member at iNEMI. He was a past President of the IEEE CPMT Society. He has been elected a Fellow of IEEE and a Fellow of ASME. He is an adjunct Professor at Binghamton University.
Janice M. Golda
Lithography Capital Equipment Development
Fab Owners Association
L.T. founded and currently serves as Executive Director of the Fab Owners Association (www.waferfabs.org), a non-profit semiconductor industry trade association and FOA Purchasing Partners, Inc., (www.waferquote.com) a Group Purchasing Organization dedicated to lowering the cost of doing business for semiconductor manufacturers and suppliers to the industry.
L.T. resides in Cupertino, California. He has had a continuous career in the sales, marketing and engineering of integrated circuits since the late 60’s, with Transitron, IBM, Zilog, VLSI Technology, Amkor Technology and Tower Semiconductor prior to starting the Fab Owners Association in 2004.
L.T has a BA degree in Business Administration and Management from Columbia Pacific University.
Vice President of Worldwide Semiconductor Packaging
Dr. Li Li
Dr. Li Li is a Distinguished Engineer at Cisco Systems, Inc. where he leads an initiative on 3D IC integration and advanced packaging development. He has been with Cisco for about 10 years and has 18 years industry experience in IC packaging design, technology development and qualification.
He led the Cisco semiconductor packaging technology team from 2007 to 2009 focusing on high performance package development and qualification for ASIC, PLD, MPU and Memory components supporting all Cisco product families including the industry leading CRS and Nexus routing and switching products. He was promoted to a Cisco Distinguished Engineer in 2008 for his outstanding contributions in advanced technology and supply chain development.
Dr. Li began his career at IBM as an Advisory Engineer. He was part of the team who developed the industry first Flip Chip Plastic Ball Grid Array (FC-BGA) for fast SRAM applications. He led a cross-functional team to develop an optoelectronics package for Philips Electronics’ Liquid Crystal on Silicon (LCOS) devices before joining Cisco System.
He is the author of several book chapters and has over 50 technical papers in the field of microelectronics packaging and currently holds 9 US patents. His technical interests include design and manufacturing of advanced packaging and interconnect products, device and package level reliability analysis, 2.5D / 3D IC integration, and System-in-Package.
Dr. Li is a Senior Member of IEEE. He currently co-chairs the Interconnections Committee for the IEEE Electronic Component Technology Conference (ECTC) and has been a member of the ECTC Program Committee since 2007. He represents Cisco on the JEDEC JC-14 and JC-42 committees and is a member of the Board of Directors at HDP User Group International, Inc. (HDPUG), an industry consortium dedicated to high-density electronic packaging. He is also active in the Assembly and Packaging Working Group for International Technology Roadmap for Semiconductors (ITRS) and 3D IC Working Group at Global Semiconductor Alliance (GSA). He volunteers to non-profit organizations in the Bay Area including Habitat for Humanity and Resource Area for Teaching (RAFT).
He received his M.S. and Ph.D. degrees in Mechanical Science and Engineering from the University of Illinois at Urbana-Champaign.
Kelvin Low joined Samsung in 2013 as senior director of marketing for the company’s foundry business. As an industry veteran, Mr. Low is responsible for the developing the strategic product direction of the foundry’s advanced process nodes – 28nm and below. In addition, he is working to develop the foundry ecosystem around these process nodes. Prior to Samsung, Mr. Low held key technical and marketing positions at GLOBALFOUNDRIES and Chartered Semiconductor Manufacturing with an emphasis on process integration and led development of logic, mixed signal, RF, CIS and NVM. Mr. Low also had additional responsibilities as the market lead in the IBM joint development alliance.
Mr. Low received his Bachelor’s degree in Electronics Engineering (First Class Honors) from the National University of Singapore.
The MAX Group
Mr. Meyuhas is a co-founder and COO of the MAX Group, a global consulting firm transforming the semiconductor industry’s operational landscape. The firm provides a unique range of operational solutions that increase factory and supply chain performance – More product out installed capital, faster cycle times, higher yields and lower cost of operation. With over 19 years of experience in the semiconductor industry, Ariel brings vision, innovation, a very strong relationship portfolio with leading semiconductors companies, and steers for perfect execution at MAX.
Dr. Gary Patton
CTO and Head of Worldwide Research and Development
Dr. Patton is the Chief Technology Officer and head of worldwide Research and Development at GLOBALFOUNDRIES. He is responsible for the company’s semiconductor technology R&D roadmap, operations, and execution.Dr. Patton was previously Vice President of IBM’s Semiconductor Research and Development Center in East Fishkill, New York. He had responsibility for IBM’s semiconductor R&D roadmap, operations, and technology development alliances, with primary locations in East Fishkill, New York, Burlington, Vermont, and the Albany Nanotech Research Center in Albany, New York. During his career at IBM, Dr. Patton has held various management and executive positions in IBM’s Microelectronics, Storage Technology, and Research Divisions, including positions in technology and product development, manufacturing, and business line management. Dr. Patton received his B.S. degree in electrical engineering from UCLA and his M.S. and Ph.D. degrees in electrical engineering from Stanford University. He is also a Fellow of the IEEE.
General Manager North America Regional Operations
Elton Peace is the General Manager of the North America Regional Operations at Lam Research, he is responsible for all Customer related activities, operations and employee development. Elton has been at Lam for 22 years and has held Key strategic roles in Field Engineering, Sales, and Customer Management. Previous to Lam Research, he held positions at Wacker Siltronic in fab operations, and Leybold Vacuum Products in field engineering and management. Elton started his career in the USAF with the Strategic Air Command, working with Electronic Countermeasures, where he learned to hide B-52 bombers from enemy radar. Elton has served on several non-profit and advisory boards over the past 32 years.
Rygler & Associates (founder of Toppan Photomasks)
ON Semiconductor Corporation
Director of Advanced Technology
Dr. John Hu is currently director of advanced technology in Nvidia Corporation. Throughout his more than 20 years career, he has worked on technical and management roles across various area of the IC industry, including semiconductor materials, device fabrications and device physics, IC process technology development, interconnect technology and 3D chip integrations, design methodology and design for manufacturing/reliability, test chips and technology driver products, and GPU/ CPU and mobile SOC technologies. John has served as the liaison for technology partnerships with various IC industry groups, companies and academics. John has also been board member of various organizations, as well as committee member and paper reviewer of technical meetings/journals. He has published more than 20 papers and has more than 10 patents granted or pending. John holds a BS degree from University of Science and Technology of China, and a Ph.D from Auburn University, in the field of solid state physics and microelectronics.